This invention relates to semiconductor integrated circuits of the type in which the electrical isolation between circuit elements comprises solid dielectric material. More particularly, it relates to complementary transistors fabricated in dielectically isolated integrated circuits for high voltage, low current use.
The control of signals in circuits in which voltage differences may reach or exceed 500 volts requires semiconductor integrated circuits with a high degree of electrical isolation. One integrated circuit structure of this type comprises an array of pockets of single crystal silicon semiconductor material supported within a conductive medium and isolated therefrom by a film of dielectric material such as silicon dioxide surrounding the sides and bottom of each pocket. The surfaces of the pockets are coplanar thus enabling making a conductive pattern interconnecting elements in the various pockets. One way of making such a structure is by forming, in one major surface of a semiconductor body, a network of grooves conforming to the desired isolation pattern between semiconductor elements of the prospective integrated circuit. In one embodiment this network is produced by anisotropic etching using etch resistant masks. A dielectric layer, such as silicon dioxide, then is deposited on the grooved surface to provide a thin but complete layer thereon. A backing layer is applied to the surface of the dielectric layer for support and its surface is made flat and parallel to the opposite major surface. Polycrystalline silicon is one preferred material for this use because it has thermal expansion properties similar to monocrystalline silicon and can be rendered conductive. The semiconductor body then is reversed and semiconductor material is removed from the opposite major surface to a depth sufficient to reach the bottom of the grooves, thereby producing an array of isolated semiconductor pockets, having a common planar surface suitable for conductive patterns interconnecting elements formed in the isolated pockets.
However, making useful complementary transistors for high voltage use in dielectrically-isolated integrated form as described above is a problem. In U.S. Pat. No. 3,895,392 there is disclosed a dielectrically-isolated semiconductor integrated circuit having complementary transistors is separate isolated pockets. However, in the high voltage switching circuits such as are disclosed in the concurrently filed application of applicants referred to hereinabove, the arrangement disclosed by U.S. Pat. No. 3,895,392 is unsuitable. In particular, the semiconductor material of the isolated pockets must be of high resistivity in order to sustain the voltage breakdown levels for the devices of interest. More particularly, the pockets all are of the same semiconductor material, in this case the original single crystal. Thus, all of the semiconductor pockets are of the same conductivity type and impurity distribution. The provision of differing conductivity type material in separate pockets presently requires complex and costly fabrication steps.
Moreover, because of the need to sustain high breakdown voltages, it is desirable to avoid the inclusion in dielectrically isolated transistors of this type of buried zones of high conductivity material within the pockets which might, in specific situations, enhance transistor performance.
Thus an object of the invention is dielectrically isolated complementary transistors having good high voltage characteristics in which the emitter, base and collector zones are all adjacent the major surface.